Title: Huffman Cache Trails – An Access Skew Aligned Cache Design Framework
Abstract: This work proposes a novel cache design that reduces energy consumption by making the switched capacitance of memory blocks inversely proportional to their data access frequency. Data sets in general purpose computing tend to have skewed access frequencies. With the rise of Big Data and Deep Learning, this trend is amplified, presenting an optimization opportunity. Traditional memory hierarchies exhibit symmetric switched capacitance at a given level, which is inefficient for energy consumption. Inspired by Huffman coding, this work introduces a novel cache organization where data sets are allocated to non-uniformly sized energy-trails, with smaller trails assigned to frequently accessed data. This reduces switched capacita
nce similarly to how Huffman coding minimizes code length. Simulations using the GEM5 simulator with SPEC 2006 CPU benchmarks show that the proposed design reduces L1D cache energy consumption by 54%, with only a 4% performance overhead.
Bio: Ananda Biswas is a PhD candidate in the Department of Electrical and Computer Engineering at Iowa State University. His research interests are in Computer Architecture, Cyber Security, and Edge AI. His published work includes novel hardware cache designs that improve the energy footprint of SRAM-based caches, as well as techniques for detecting and mitigating control flow hijack attacks in IoT devices. Outside of academia, Ananda enjoys biking, cooking, working on his old car, and reading about the origins of science.
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