Title: Power-Efficient High-Resolution ADCs for Broadband Applications
Speaker: Jose Silva-Martinez, Texas Instruments Professor, Texas A&M University
Abstract: The telecommunications technology trend is towards mobile wireless communications systems; the “All in One” mobile systems are clearly becoming the preferred source of communication. For instance, emerging Long-Term Evolution (LTE) standards for the next generation of cellular phones have been developed to allocate more and faster services. Wideband digitization is also needed for the demodulation of multiple TV channels, which demands an effective ADC bandwidth up to 850MHz with over 10 ENOB. This ever growing need for the digitization of wider bandwidth signals demands better linearity figures since the ADC input power increases due to the extra channels; this performance improvement, however, should not be at the expense of higher power consumption. Portable devices are highly preferred by consumers who appreciate mobile multimedia experience, but also demand longer battery runtime.
In this scenario, the ADC linearity is quite critical; otherwise, large blockers may be aliased within the bandwidth of the desired channels limiting the quality of the received signal. The technology roadmap shows that scaling up the ADC resolution by 1 bit may require up to 4x power increase. This trend leads to impractical power levels that have restricted the adoption of high-frequency, high-resolution ADCs, since they do not contribute to greener consumer electronic devices. For example, the solution offered by Texas Instruments providing a signal bandwidth up to 1.9 GHz bandwidth and 9 ENOB dissipates over 4 Watts. The goal of this effort is to develop an unmatched time interleave ADC architecture that employs 4 pipeline sub-ADCs, running at 500 MS/s each, to achieve a resolution of 12 ENOB at 2GS/s while power dissipation is under 500mWatts. This would be possible by leveraging on a very fast technology such as TSMC 40nm vanilla CMOS, the development of efficient calibration scheme for linearity, magnitude and timing mismatches between the sub-ADCs, and the use of innovative IC design techniques suitable for high-resolution low-power broadband applications. In this seminar, 3 recent ADCs experimentally verified in the laboratory are described. A full digital calibration scheme for high-performance SD modulators is described, after that a 75MHz 28mW 11 ENOB SM is briefly discussed. Finally, a pipeline ADC architecture fabricated in 40nm technology will be introduced.
Speaker Bio: Jose Silva-Martinez is a faculty member in the Department of Electrical and Computer Engineering at Texas A&M University where he holds the position of Texas Instruments Professor. He is an IEEE Fellow, has been actively involved with the organization of several conferences, and is actively involved with the IEEE Circuits and Systems Society. He has co-authored over 110 journal papers, over 160 conference papers, 2 books, and 12 book chapters. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical applications.
Dr. Silva-Martinez is currently serving as the Editor in Chief of the IEEE Transactions on Circuits and Systems (TCAS) Part-II and is also serving as the Associate Department Head for Graduate Studies in the ECE Department at Texas A&M.