Index

NameLast modifiedSize
Parent Directory  -
02_Binary_Numbers.ppt2013-08-30 15:21 4.9M
03_Logic_Gates.ppt2013-08-30 15:21 4.3M
04_No_Class.ppt2013-09-08 17:02 118K
05_Boolean_Algebra.ppt2013-09-08 17:03 3.5M
06_Synthesis.ppt2013-09-08 17:03 2.5M
07_NAND_and_NOR.ppt2013-09-11 16:02 5.0M
08_Design_Examples.ppt2013-09-11 16:02 2.3M
09_Verilog_part1.ppt2013-09-13 17:06 2.8M
10_Verilog_part2.pptx2013-09-25 17:22 114K
11_K-Maps.ppt2013-09-25 17:23 848K
12_Minimization.ppt2013-09-25 17:23 1.6M
13_Functions_and_Circuits.ppt2013-09-25 17:23 1.5M
14_Examples.ppt2013-09-25 17:23 2.2M
15_Midterm_Review.ppt2013-10-04 19:43 139K
16_Midterm1_No_Lecture.ppt2013-10-04 19:43 118K
17_Addition_of_Unsigned_Numbers.ppt2013-10-04 19:43 1.2M
18_Signed_Numbers.ppt2013-10-04 19:44 2.1M
19_Fast_Adders.ppt2013-10-14 17:32 2.1M
20_Floating_Point_Numbers.ppt2013-10-14 17:32 2.8M
21_Multiplication.ppt2013-10-14 17:32 723K
22_Multiplexers.ppt2013-10-14 17:33 1.9M
23_Decoders_and_Encoders.ppt2013-10-18 17:08 2.0M
24_Code_Converters.ppt2013-10-18 17:08 1.0M
25_Latches.ppt2013-10-25 19:08 2.9M
26_D_Flip-Flops.ppt2013-10-25 19:08 1.3M
27_Midterm_Review.ppt2013-10-25 19:09 139K
28_Midterm2_No_Lecture.ppt2013-10-25 19:10 118K
29_T_Flip-Flops.ppt2013-11-01 17:22 764K
30_JK_Flip-Flops.ppt2013-11-01 17:23 531K
31_Registers.ppt2013-11-17 18:43 1.1M
32_Counters.ppt2013-11-17 18:36 1.0M
33_Solved_Problems.ppt2013-11-17 18:10 916K
34_Basic_Design_Steps.ppt2013-11-17 18:12 696K
35_State_Assignment_Problem.ppt2013-11-17 18:14 2.3M
37_Mealy_State_Model.ppt2013-11-18 17:27 1.6M
38_Serial_Adder.ppt2013-12-06 18:44 504K
39_State_Minimization.ppt2013-12-06 19:17 1.5M
40_Designing_a_Counter.ppt2013-12-06 18:45 3.6M
41_Arbiter_Circuit.ppt2013-12-06 18:45 407K
42_Analysis_of_SSC.ppt2013-12-06 18:45 3.1M
43_ASM_Charts.ppt2013-12-11 19:29 1.3M
44_Register_Machines.ppt2013-12-11 19:28 30M
45_Final_Review.ppt2013-12-13 21:47 7.8M