Index

NameLast modifiedSize
Parent Directory  -
02_Binary_Numbers.ppt2015-08-26 15:11 4.9M
03_Logic_Gates.ppt2015-08-28 15:41 3.0M
04_Boolean_Algebra.ppt2015-08-31 17:00 3.5M
05_Synthesis.ppt2015-09-04 16:02 2.7M
06_NAND_and_NOR.ppt2015-09-09 14:56 8.2M
07_No_Class.ppt2015-09-09 14:30 118K
08_Design_Examples.ppt2015-09-09 14:54 7.4M
09_Intro_to_Verilog.ppt2015-09-11 16:00 8.1M
10_K-Maps.ppt2015-09-14 15:58 2.0M
11_Minimization.ppt2015-09-18 12:25 2.2M
12_Functions_and_Circuits.ppt2015-09-18 12:25 4.3M
13_Examples.ppt2015-09-23 17:36 2.6M
14_Midterm_Review.ppt2015-09-23 17:37 139K
15_Midterm1_No_Lecture.ppt2015-09-23 17:37 118K
16_Addition_of_Unsigned_Numbers.ppt2015-09-30 15:22 1.3M
17_Signed_Numbers.ppt2015-09-30 16:02 2.5M
18_Fast_Adders.ppt2015-10-07 16:05 4.0M
19_Multiplication.ppt2015-10-07 16:04 6.9M
20_Floating_Point_Numbers.ppt2015-10-07 14:51 2.9M
21_Multiplexers.ppt2015-10-12 15:55 2.5M
22_Decoders_and_Encoders.ppt2015-10-14 15:46 2.5M
23_Code_Converters.ppt2015-10-16 14:14 1.5M
24_Latches.ppt2015-10-16 15:56 5.8M
25_D_Flip-Flops.ppt2014-10-22 16:01 1.4M
26_T_and_JK_Flip-Flops.ppt2015-10-22 14:49 536K
27_Registers.ppt2015-10-26 15:48 3.0M
28_Counters.ppt2015-10-26 15:43 2.6M
29_Midterm_Review.ppt2014-10-20 14:07 139K
30_Midterm2_No_Lecture.ppt2014-10-20 14:07 118K
31_Solved_Problems.ppt2015-11-02 15:51 1.8M
32_Basic_Design_Steps.ppt2015-11-04 14:27 2.3M
33_State_Assignment_Problem.ppt2015-11-06 17:16 6.0M
34_Mealy_State_Model.ppt2015-11-09 15:53 1.6M
35_Serial_Adder.ppt2015-11-11 10:11 4.7M
36_State_Minimization.ppt2015-11-13 16:05 2.2M
37_Designing_a_Counter.ppt2015-11-16 17:16 3.7M
38_Analysis_of_SSC.ppt2015-11-18 15:34 3.3M
39_Arbiter_Circuit.ppt2014-11-21 17:13 701K
40_ASM_Charts.ppt2015-12-02 13:44 6.3M
41_Register_Machines.ppt2015-12-02 11:52 30M
43_Simple_Processor.ppt2015-12-07 15:22 6.6M
44_Simple_Processor_part2.ppt2015-12-09 17:37 6.7M
45_Final_Review.ppt2015-12-11 15:51 8.7M