Analysis & Synthesis report for lab1step3 Wed Jun 08 15:47:11 2016 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. General Register Statistics 9. Post-Synthesis Netlist Statistics for Top Partition 10. Elapsed Time Per Partition 11. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+---------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Wed Jun 08 15:47:11 2016 ; ; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Lite Edition ; ; Revision Name ; lab1step3 ; ; Top-level Entity Name ; lab1step3 ; ; Family ; Cyclone IV E ; ; Total logic elements ; 1 ; ; Total combinational functions ; 1 ; ; Dedicated logic registers ; 0 ; ; Total registers ; 0 ; ; Total pins ; 4 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+---------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP4CE115F29C7 ; ; ; Top-level entity name ; lab1step3 ; lab1step3 ; ; Family name ; Cyclone IV E ; Cyclone IV GX ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; ; Synthesis Seed ; 1 ; 1 ; +----------------------------------------------------------------------------+--------------------+--------------------+ Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 4 ; ; Maximum allowed ; 1 ; +----------------------------+--------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------------------------+--------------------------------------------------------------------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +----------------------------------+-----------------+------------------------------------------+--------------------------------------------------------------------------------------------------+---------+ ; lab1step3.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; C:/Users/Scott/Box Sync/ISU_Work/CPRE281/Lab/Lab01/DE2-115 CPRE281 LAB01/lab1step3/lab1step3.bdf ; ; +----------------------------------+-----------------+------------------------------------------+--------------------------------------------------------------------------------------------------+---------+ +-------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+---------+ ; Resource ; Usage ; +---------------------------------------------+---------+ ; Estimated Total logic elements ; 1 ; ; ; ; ; Total combinational functions ; 1 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 0 ; ; -- 3 input functions ; 1 ; ; -- <=2 input functions ; 0 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 1 ; ; -- arithmetic mode ; 0 ; ; ; ; ; Total registers ; 0 ; ; -- Dedicated logic registers ; 0 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 4 ; ; ; ; ; Embedded Multiplier 9-bit elements ; 0 ; ; ; ; ; Maximum fan-out node ; inst4~0 ; ; Maximum fan-out ; 1 ; ; Total fan-out ; 8 ; ; Average fan-out ; 0.89 ; +---------------------------------------------+---------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+ ; |lab1step3 ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; |lab1step3 ; lab1step3 ; work ; +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 0 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 0 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-----------------------------------------------------+ ; Post-Synthesis Netlist Statistics for Top Partition ; +-----------------------+-----------------------------+ ; Type ; Count ; +-----------------------+-----------------------------+ ; boundary_port ; 4 ; ; cycloneiii_lcell_comb ; 1 ; ; normal ; 1 ; ; 3 data inputs ; 1 ; ; ; ; ; Max LUT depth ; 1.00 ; ; Average LUT depth ; 1.00 ; +-----------------------+-----------------------------+ +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ ; Top ; 00:00:00 ; +----------------+--------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition Info: Processing started: Wed Jun 08 15:46:49 2016 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab1step3 -c lab1step3 Warning (20028): Parallel compilation is not licensed and has been disabled Warning (12125): Using design file lab1step3.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info (12023): Found entity 1: lab1step3 Info (12127): Elaborating entity "lab1step3" for the top level hierarchy Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Info (21057): Implemented 5 device resources after synthesis - the final resource count might be different Info (21058): Implemented 3 input pins Info (21059): Implemented 1 output pins Info (21061): Implemented 1 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings Info: Peak virtual memory: 798 megabytes Info: Processing ended: Wed Jun 08 15:47:11 2016 Info: Elapsed time: 00:00:22 Info: Total CPU time (on all processors): 00:00:52