Classic Timing Analyzer report for lab1step3 Thu Aug 26 11:28:16 2010 Quartus II 64-Bit Version 10.0 Build 218 06/27/2010 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Classic Timing Analyzer Deprecation 3. Timing Analyzer Summary 4. Timing Analyzer Settings 5. Parallel Compilation 6. tpd 7. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. --------------------------------------- ; Classic Timing Analyzer Deprecation ; --------------------------------------- Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents. +-----------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Summary ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ ; Worst-case tpd ; N/A ; None ; 6.904 ns ; B ; F ; -- ; -- ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; +------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Settings ; +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ ; Option ; Setting ; From ; To ; Entity Name ; +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ ; Device Name ; EP2C35F672C6 ; ; ; ; ; Timing Models ; Final ; ; ; ; ; Default hold multicycle ; Same as Multicycle ; ; ; ; ; Cut paths between unrelated clock domains ; On ; ; ; ; ; Cut off read during write signal paths ; On ; ; ; ; ; Cut off feedback from I/O pins ; On ; ; ; ; ; Report Combined Fast/Slow Timing ; Off ; ; ; ; ; Ignore Clock Settings ; Off ; ; ; ; ; Analyze latches as synchronous elements ; On ; ; ; ; ; Enable Recovery/Removal analysis ; Off ; ; ; ; ; Enable Clock Latency ; Off ; ; ; ; ; Use TimeQuest Timing Analyzer ; Off ; ; ; ; ; Minimum Core Junction Temperature ; 0 ; ; ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; ; ; Number of source nodes to report per destination node ; 10 ; ; ; ; ; Number of destination nodes to report ; 10 ; ; ; ; ; Number of paths to report ; 200 ; ; ; ; ; Report Minimum Timing Checks ; Off ; ; ; ; ; Use Fast Timing Models ; Off ; ; ; ; ; Report IO Paths Separately ; Off ; ; ; ; ; Perform Multicorner Analysis ; On ; ; ; ; ; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; ; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ; ; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ; ; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; ; 2-4 processors ; 0.0% ; +----------------------------+-------------+ +---------------------------------------------------------+ ; tpd ; +-------+-------------------+-----------------+------+----+ ; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; +-------+-------------------+-----------------+------+----+ ; N/A ; None ; 6.904 ns ; B ; F ; ; N/A ; None ; 6.728 ns ; C ; F ; ; N/A ; None ; 6.593 ns ; A ; F ; +-------+-------------------+-----------------+------+----+ +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit Classic Timing Analyzer Info: Version 10.0 Build 218 06/27/2010 SJ Full Version Info: Processing started: Thu Aug 26 11:28:15 2010 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lab1step3 -c lab1step3 --timing_analysis_only Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents. Info: Parallel compilation is enabled and will use 4 of the 4 processors detected Info: Longest tpd from source pin "B" to destination pin "F" is 6.904 ns Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 1; PIN Node = 'B' Info: 2: + IC(0.369 ns) + CELL(0.438 ns) = 1.806 ns; Loc. = LCCOMB_X64_Y19_N16; Fanout = 1; COMB Node = 'inst4~0' Info: 3: + IC(2.340 ns) + CELL(2.758 ns) = 6.904 ns; Loc. = PIN_Y18; Fanout = 0; PIN Node = 'F' Info: Total cell delay = 4.195 ns ( 60.76 % ) Info: Total interconnect delay = 2.709 ns ( 39.24 % ) Info: Quartus II 64-Bit Classic Timing Analyzer was successful. 0 errors, 1 warning Info: Peak virtual memory: 264 megabytes Info: Processing ended: Thu Aug 26 11:28:16 2010 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00