Index

NameLast modifiedSize
Parent Directory  -
02_Binary_Numbers.ppt2017-08-21 15:42 3.9M
03_Logic_Gates.ppt2017-08-25 12:57 2.9M
04_Boolean_Algebra.ppt2017-08-28 15:55 3.3M
05_Synthesis.ppt2017-09-01 15:38 2.6M
06_NAND_and_NOR.ppt2017-09-01 15:36 8.2M
07_No_Class.ppt2017-09-05 21:31 99K
08_Design_Examples.ppt2017-09-06 18:17 8.5M
09_Intro_to_Verilog.ppt2017-09-08 13:29 6.6M
10_K-Maps.ppt2017-09-15 15:55 1.7M
11_Minimization.ppt2017-09-15 15:56 2.3M
12_Functions_and_Circuits.ppt2017-09-18 15:54 4.3M
13_Examples.ppt2017-09-18 15:47 2.2M
14_Midterm_Review.ppt2017-09-18 15:03 99K
15_Midterm1_No_Lecture.ppt2017-09-18 15:02 99K
16_Addition_of_Unsigned_Numbers.ppt2017-09-29 12:23 1.2M
17_Signed_Numbers.ppt2017-09-29 12:25 3.3M
18_Fast_Adders.ppt2017-09-29 15:58 5.4M
19_Multiplication.ppt2017-10-02 15:58 7.4M
20_Floating_Point_Numbers.ppt2017-10-04 16:00 2.1M
21_Multiplexers.ppt2017-10-05 19:29 2.3M
22_Decoders_and_Encoders.ppt2017-10-11 16:00 4.2M
23_Code_Converters.ppt2017-10-11 16:03 3.3M
24_Latches.ppt2017-10-13 16:03 5.8M
25_D_Flip-Flops.ppt2017-11-06 09:48 2.5M
26_T_and_JK_Flip-Flops.ppt2017-10-20 15:18 1.1M
27_Registers.ppt2017-10-20 21:00 3.3M
28_Counters.ppt2017-11-05 21:25 3.2M
29_Midterm_Review.ppt2017-10-31 17:07 99K
30_Midterm2_No_Lecture.ppt2017-10-31 17:07 99K
31_Solved_Problems.pptx2017-11-05 21:26 2.8M
32_Basic_Design_Steps.ppt2017-11-01 17:08 2.5M
33_State_Assignment_Problem.ppt2017-11-06 15:53 10M
34_Mealy_State_Model.ppt2017-11-06 15:49 1.6M
35_Serial_Adder.ppt2017-11-08 15:57 4.8M
36_State_Minimization.ppt2017-11-07 17:21 1.8M
37_Designing_a_Counter.ppt2017-11-07 17:36 3.6M
38_Analysis_of_SSC.ppt2017-11-08 09:27 3.0M
39_Arbiter_Circuit.ppt2017-11-17 15:49 783K
40_ASM_Charts.ppt2017-11-27 14:18 6.4M
41_Register_Machines.ppt2017-11-29 15:38 2.4M
43_Simple_Processor.ppt2017-12-01 14:55 5.2M
44_Simple_Processor_part2.ppt2017-12-06 15:54 5.2M
45_Final_Review.ppt2017-12-08 13:04 5.8M