Index

NameLast modifiedSize
Parent Directory  -
02_Binary_Numbers.ppt2018-08-22 16:02 3.9M
03_Logic_Gates.ppt2018-08-24 15:16 2.9M
04_Boolean_Algebra.ppt2018-08-29 11:00 3.3M
05_Synthesis.ppt2018-08-29 15:56 2.6M
06_NAND_and_NOR.ppt2018-08-31 11:48 8.2M
07_No_Class.ppt2018-09-05 15:47 103K
08_Design_Examples.ppt2018-09-05 15:50 8.5M
09_Intro_to_Verilog.ppt2018-09-07 15:48 6.6M
10_K-Maps.ppt2018-09-10 15:36 1.9M
11_Minimization.ppt2018-09-12 15:56 2.0M
12_Functions_and_Circuits.ppt2018-09-14 15:56 4.0M
13_Examples.ppt2018-09-17 15:56 2.2M
14_Midterm_Review.ppt2018-09-24 15:37 103K
15_Midterm1_No_Lecture.ppt2018-09-24 15:38 100K
16_Addition_of_Unsigned_Numbers.ppt2018-09-24 15:08 1.1M
17_Signed_Numbers.ppt2018-09-28 16:06 3.3M
18_Fast_Adders.ppt2018-09-28 16:04 6.3M
19_Multiplication.ppt2018-10-01 16:07 7.4M
20_Floating_Point_Numbers.ppt2018-10-03 15:47 2.1M
21_Multiplexers.ppt2018-10-05 13:47 2.2M
22_Decoders_and_Encoders.ppt2018-10-12 15:41 5.2M
23_Code_Converters.ppt2018-10-12 15:39 4.3M
24_Latches.ppt2018-10-12 15:35 5.8M
25_D_Flip-Flops.ppt2018-10-15 15:58 2.5M
26_T_and_JK_Flip-Flops.ppt2018-10-17 15:53 1.1M
27_Registers.ppt2018-10-19 16:03 4.1M
28_Counters.ppt2018-10-22 16:03 2.6M
29_Midterm_Review.ppt2018-10-29 23:13 103K
30_Midterm2_No_Lecture.ppt2018-10-29 23:14 100K
31_Solved_Problems.pptx2018-10-29 16:04 2.8M
32_Basic_Design_Steps.ppt2018-10-30 19:11 2.5M
33_State_Assignment_Problem.ppt2018-11-02 18:19 11M
34_Mealy_State_Model.ppt2018-11-02 18:21 1.6M
35_Serial_Adder.ppt2018-11-02 18:22 4.9M
36_State_Minimization.ppt2018-11-09 13:45 1.9M
37_Designing_a_Counter.ppt2018-11-12 16:01 3.6M
38_Analysis_of_SSC.ppt2018-11-14 15:54 3.0M
39_Arbiter_Circuit.ppt2018-11-16 11:01 801K
40_ASM_Charts.ppt2018-11-26 15:55 7.0M
41_Register_Machines.ppt2018-11-28 16:02 2.4M
43_Simple_Processor.ppt2018-12-03 16:02 5.3M
44_Simple_Processor_part2.ppt2018-12-05 14:39 5.3M
45_Final_Review.ppt2018-12-07 16:07 5.9M