CprE / ComS 583
Reconfigurable Computing
Fall 2006
Project
The goal of this project is for you to gain an in-depth understanding of some aspect of reconfigurable computing. Students will work in groups of 2-3 people, and will be expected to deliver a detailed proposal and final report, along with a presentation summarizing the project to the rest of the class. Each project must contain an element of design and experimentation; proposals that do not meet this criterion will be rejected.
Deliverables
- Proposal (2-3 pages, due week after midterm exam). This should include an introduction, a discussion of related work, and a discussion of your proposed approach. It should also detail specific design and experimentation methodologies where appropriate.
- Presentation (25 minutes, due last week of classes). On-campus students will be expected to present a summary of their findings to the rest of the class. Distance education students will be expected to provide the files and whatever notes would be required to give a presentation on their topic.
- Final Report (8-12 pages, due final exam week). See the proceedings of conferences like FPGA, FCCM, and FPL for examples of how to write papers on various topics in reconfigurable computing.
Some Suggested Topics
- Design and implementation of X application
- Pick any application or application domain
- Identify whatever objectives need to optimized (power, performance, area, etc.)
- Design and implement X targeting an FPGA
- Compare to microprocessor-based implementations
- Network processing
- Explore the use of an FPGA as a network processor that can support flexibility in protocol through reconfiguration
- Flexibility could be with respect to optimization
- Could provide additional processing to packets/connections
- Implement a full-fledged FPGA-based embedded system
- From block diagram to physical hardware
- Examples:
- Image/video processing
- Digital picture frame
- Digital clock (w/video)
- Sound effects processor
- Any old-school video game :)
- Voice-over-IP
- Prototype some microarchitectural concept using FPGA
- See proceedings of MICRO/ISCA/HPCA/ASPLOS from last 5 years
- Survey some recurring theme
- Compare results from simulation (Simplescalar) to FPGA prototype results
- Evaluation of various high-level synthesis tools and methodologies
- Survey 4-5 different open-source high-level synthesis tools
- Pick a representative (pre-existing) benchmark set, see how they fare...how well do they work?
- Compare to microprocessor-based implementation of same
- Anything else that interests you!
Previous Year's Topics
- The Virtex 2 and 4 block RAMs can be deployed as augmenting I-cache or D-cache. Develop a microarchitecture cache control mechanism that decides when additional D-cache or I-cache would be beneficial. Develop a schema to employ a large chunk of DSOCM and/or ISOCM as additional D-cache or I-cache. Evaluate the effectiveness of this architecture vis a vis the fixed cache size architecture through a mix of architecture level and Modelsim based simulations.
- Build a decoupled architecture out of two PPC cores in V4. A decoupled architecture runs two (or more) instructions streams that synchronize with respect to each other. Look at a branch decoupling paper as an example of a decoupled architecture.
- The memory bandwidth (and time) needed for configuration and reconfiguration is a major bottleneck in reconfigurable computing. Does it make sense to develop on-chip configuration generators? If yes, what kind of architecture should this configuration generator have? Evaluate the scheme.
- opencores.org has an implementation of JVM (JOP) at its web site. The objective in this project is to assess the effectiveness of object caching (both its data and method part) into the block RAMs of the FPGA.
- Pattern matching algorithms play a large role in both computational biology and in intrusion detection systems. FPGAs have been used in both these domains to speed up the pattern matching tasks. Implement a specific pattern matching algorithm and evaluate its speed up compared to a software only solution.
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Copyright © 2006 by Joseph Zambreno. All rights reserved. |